The present invention relates to a system for testing digital logic systems.
Digital logic simulation is a technique utilized to verify and debug a logic system which is designed before it is fabricated. Simulation techniques are also utilized to experiment with a given design so that appropriate design modifications and choices can be made without the expense of actually constructing the design. In the past computer software has been used to simulate many types of designs but at a performance speed which is many orders of magnitude lower than real time operation. The speed of such software simulations systems can be increased by providing a hybrid software/hardware system. An example of one such simulator is that used to simulate the operation of an aircraft.
Digital logic systems have traditionally been simulated in software at the subsystem level but not at the system level except when the cost of a mistake in the final system cannot be tolerated. In many cases, digital logic which is to be fabricated on a LSI or VLSI chip has been prefabricated using discrete components or other small scale integrated devices in order to test the design. For example, in the past, SSI chips have been mounted on PC boards in place of each of the LSI chips contemplated for a final computer design. A model of the computer would be built with these PC boards and used to debug the design. Such a simulation technique is time consuming, expensive and itself generates defects not normally found in an LSI or VLSI chip.
More recently, the algorithms used by the software simulators have been implemented in hardware which can operate one or two orders of magnitude faster and cost one or two orders of magnitude less than software techniques. Examples of such systems are disclosed in Blum (U.S. Pat. No. 4,428,060) and Von Brunt (U.S. Pat. No. 4,527,249).
Conventional simulation techniques are typically called event driven simulators. As exemplified by that illustrated in the Blum '060 patent each gate is simulated that has an input change. The propagation times through the gate are also monitored. If a gate changes state, this causes a new event to occur. The simulator must maintain a list of events and flag the gates driven by these events for evaluation. An event driven simulator can simulate both event driven, i.e., nonsynchronous, and synchronous logic designs. In most digital systems, only about 20% of the gates change state in any given clock cycle and accordingly an event driven simulator does not have to simulate all of the gates at each interval time.
In a synchronous design with level sensitive logic, there are no feedback loops or so-called race conditions such that the difference in path delay may cause a pulse which can be used as an event for causing further switching to occur. Thus in a synchronous system, at each clock cycle, data is transmitted from latches to the logic gate connected directly to the latches. These gates may switch causing new inputs to the next gate in the path which may also switch resulting in an orderly propagation of data to the input of the next set of latches. This logic can be simulated by first evaluating all the gates with inputs connected only to the output of the latches. Then the gates one logic level away from the latches are evaluated, then two levels away, and so on until all the logic is evaluated.
Instructions to simulate this logic can be placed in a sequence determined by the level of the logic gate in the data path. In this sequence, one pass of the instructions will evaluate all of the gates and determine the inputs to the next latches. No decision must be made to evaluate a gate and no status table need be maintained. Accordingly the instructions can be executed in a "pipeline" sequence with no branches. When all the gates have been evaluated, the inputs to the latches are stored in memory locations associated with the master portion of the latches. This data is then transferred to memory locations associated with the slave portion of the latches to simulate the action of the master clock. Thus, only one pass through of the instructions and one exchange of master/slave data simulates one clock cycle of the synchronous design.
This levelized form of simulation requires less than eight computer instructions to simulate each gate. Thus, in a one MIP computer this results in a simulation rate of 120,000 gates per second. Even though the levelized simulator is evaluating every gate per system cycle compared to the typical 20% evaluation for an event driven simulator, it is still ten times faster than the event driven simulator.
It accordingly is an object of the present invention to provide an improved logic simulation system.